1. Field of the Invention
The present invention relates generally to a redundancy efficiency increasing circuit of semiconductor memory device and, more particularly, to a redundancy efficiency increasing circuit of semiconductor memory device which can increase efficiency of redundancy twice by using unused fuse having a block fail when a block fail is generated, thereby only a half of chip is used.
2. Description of the Related Art
FIG. 1 shows generally the column redundancy structure in a conventional semiconductor memory device. In FIG. 1, only two memory banks, labeled as Bank i and Bank k, are used in describing the conventional column redundancy structure although more than two memory banks may be used. Each memory bank (either Bank i or Bank k) includes four memory blocks, one of which is shown with a reference label 10 in FIG. 1. Further, in each memory bank Bank i or Bank k, there are two column redundancy lines RYS0 and RYS1. Up to two column fails (occurring, for example, while accessing the data in the memory block) are recoverable in any one of the memory blocks 10 by allowing one of the two column redundancy lines RYS0 or RYS1 to substitute for the other column redundancy line. The same operations of column redundancy line substitutions in the event of a column fail is also performed in the other remaining memory blocks 10 in the same memory bank, Bank i or Bank k. According to this conventional column redundancy structure, only up to two column fails are recoverable in any one conventional memory bank, Bank i or Bank k.
Associated with each bank, Bank i or Bank k, a redundancy control block 30 having a Y fuse 20 is provided to control and oversee the column fail recovery operation in each memory bank Bank i or Bank k. The column fail recovery operations for the column line substitution operations are performed based at least on the signals for comparing the Y address, AY<0:m>, the signals for bank coding BAi, and the signals for X block coding Bxi<0:n> that are inputted to redundancy control block 30 as shown in FIG. 1. However, in the event of an unrecoverable block fail in a memory bank (e.g., Bank k) due to, for example, more than two unrecoverable column fails generated in a memory bank, the other bank, Bank i, could only be used. As already discussed above, recovering from more than two column fails in one memory bank 10 of a conventional column redundancy structure as shown FIG. 1 is not possible. Therefore, the Y fuse of a failed memory bank (for example, of the Bank k) cannot be used for any other operational memory bank(s) such as the Bank i in FIG. 1.